A circuit generally comprising a plurality of master modules and a supervisor module is disclosed. The supervisor module may be configured to (i) detect a target address and a particular master module of the master modules initiating a transaction on a bus, (ii) identify a predetermined authorization in response to the particular master module, the target address and a current security mode of at least three security modes and (iii) subvert the transaction in response to the predetermined authorization restricting the transaction.

 
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> Precise exit logic for removal of security overlay of instruction space

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