Input pipeline registers are provided at inputs to functional units and
data paths in a adaptive computing machine. Input pipeline registers are
used to hold last-accessed values and to immediately place commonly
needed constant values, such as a zero or one, onto inputs and data
lines. This approach can reduce the time to obtain data values and
conserve power by avoiding slower and more complex memory or storage
accesses. Another embodiment of the invention allows data values to be
obtained earlier during pipelined execution of instructions. For example,
in a three stage fetch-decode-execute type of reduced instruction set
computer (RISC), a data value can be ready from a prior instruction at
the decode or execute stage of a subsequent instruction.