A system includes a memory unit and a processor where the processor has a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache controller until load data for load operations prior to the first instruction fetched from the memory unit are globally observed. The processor further may include a control register having a first mode storage to store a mode control selection for pre-serialization and a second mode storage to store a mode control selection for post-serialization to enable control of pre-serialization and post-serialization of load operations with respect to the first instruction. Other embodiments are described and claimed.