A system and method of dynamic offset compensation that is particularly adaptable to analog-to-digital conversion performed in control applications employing highly integrated Digital Signal Processor (DSP) devices. The system providing dynamic compensation of Analog-to-Digital Converter (ADC) zero level offset errors includes an integrated DSP device with a multi-bit ADC and a PWM waveform generator for producing at least one PWM output, and an external low pass filter. The ADC receives an analog input signal and converts it into a corresponding digital output signal. The DSP device measures the zero level offset of the ADC output signal, and dynamically controls characteristics of the PWM output based on the measured offset. The low pass filter receives the PWM output and applies a corresponding controlled DC output voltage to the low reference voltage input of the ADC to dynamically compensate for the zero level offset error.