An Integrated Circuit Design tool incorporating a Stochastic Analysis
Process ("SAP") is described. The SAP can be applied on many levels of
circuit components including transistor devices, logic gate devices, and
System-on-Chip or chip designs. The SAP replaces a large number of
traditional Monte Carlo simulations with operations using a small number
of sampling points or corners. The SAP is a hierarchical approach using a
model fitting process to generate a model that can be used with any
number of performance memos to generate performance variation predictions
along with corresponding statistical information (e.g., mean, three-sigma
probability, etc.). The SAP provides an efficient way of modeling the
circuit or system variation due to global parameters such as device
dimensions, interconnect wiring variations, economic variations, and
manufacturing variations.