A cross-point RRAM memory array includes a word line array having an array of substantially parallel word lines therein and a bit line array having an array of substantially parallel bit lines therein, wherein said bit lines are substantially perpendicular to said word lines, and wherein a cross-point is formed between said word lines and said bit lines. A memory resistor located between said word lines and said bit lines at each cross-point. A high-open-circuit-voltage gain, bit line sensing differential amplifier circuit located on each bit line, including a feedback resistor and a high-open-circuit-voltage gain amplifier, arranged in parallel, wherein a resistance of the feedback resistors is greater than a resistance of any of the memory resistors programmed at a low resistance state.