In a computer system, an I/O adapter comprises at least one I/O request mailbox for receiving I/O requests and data from a CPU. The mailbox is connected to at least one I/O request queue storage for storing a plurality of I/O requests and related data or main memory addresses received by the mailbox. A credit register is provided for storing the filling state of the queue storage. A connection network is designed and operated to transfer the contents of the credit register to the CPU for checking the filling state of the queue storage, to transfer an I/O request and related data to a queue of a selected request mailbox, and to activate a doorbell apparatus for signalling to the I/O adapter to process the I/O request including an access to the main memory by the I/O adapter if required.

 
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> Computer system architecture for a processor connected to a high speed bus transceiver

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