A dielectric layer (50) is formed over a semiconductor (10) that contains
a first region (20) and a second region (30). A polysilicon layer is
formed over the dielectric layer (50) and over the first region (20) and
the second region (30). The polysilicon layer can comprise 0 to 50 atomic
percent of germanium. A metal layer is formed over the polysilicon layer
and one of the regions and reacted with the underlying polysilicon layer
to form a metal silicide or a metal germano silicide. The polysilicon and
metal silicide or germano silicide regions are etched to form transistor
gate regions (60) and (90) respectively. If desired a cladding layer
(100) can be formed above the metal gate structures.