A method and apparatus are provided for placing cells in an integrated
circuit layout pattern. A base layer layout pattern defines an array of
base cell locations and base layer elements, wherein at least portions of
some rows in the array are reserved for decoupling capacitor cells. Each
decoupling capacitor cell has a width, which is greater than that of a
single base cell location and which is abstracted from the base layer
layout pattern. A cell library defines a plurality of cells, including a
macro cell having open rows consistent with the rows in the base layer
layout pattern that are reserved for the decoupling capacitor cells. The
width of each decoupling capacitor cell is abstracted from the macro
cell. Cells from the cell library, including the macro cell, are placed
within a design layout pattern relative to the base layer layout pattern.
An area consumed by the macro cell within the design layout pattern is
independent of the width of the decoupling capacitor cells.