A clock tree synthesis (CTS) apparatus, generator, and method for synthesizing a clock tree includes a plurality of clock signal generators that output different clock signals generated from a reference clock signal. The clock signal generators includes an additional logic circuit that is not recognized as an end point of the reference clock signal when the clock tree is synthesized. In one example, the clock signal generator is a flip-flop and the additional logic circuit is a tri-state buffer.

 
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> Method, system, and article of manufacture for implementing metal-fill with power or ground connection

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