A wake-up reset circuit is provided that generates a reset signal to a
digital circuit upon a wake-up event. The wake-up reset circuit places
the digital circuit into a known reset condition upon wake-up, even if a
brown out condition occurs which may have caused unstable and unknown
logic states in sequential circuit elements, e.g., volatile memory, flip
flops and/or latching circuits. The wake-up reset circuit draws
substantially no current when not generating the reset signal.