A method to handle data dependencies in a pipelined computer system is disclosed. The method includes allocating a plurality of registers, enabling execution of computer instructions concurrently by using the plurality of registers, and tracking and reducing data dependencies in the computer instructions by correlating a busy condition of a computer instruction to each register.

 
Web www.patentalert.com

> Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture

~ 00353