The present invention provides an image decoding apparatus that realizes
speed-up processing of taking out an MR (macroblock remainder) from a
fixed length unit that consists of a first DCT block and the MR, without
increasing cost. A Setup processor 3 outputs one out of a plurality of
fixed length units that constitute an SB (synchronized block). First,
calculation is performed for a length from a beginning of the fixed
length unit to a EOB (end of block) that is included in the fixed length
unit. The calculated length is then used as an offset in taking out the
MR. Then an end portion of a second DCT block that is included in the MR
is combined with a corresponding beginning portion of the second DCT
block, in order to obtain the complete second DCT block. The complete
second DCT block is outputted to a variable length code decoder 13.