Certain embodiments of the invention may be found in a method and system for monitoring a set of semaphore registers using a limited-width test bus. Each semaphore register represents a separate hardware resource. The bits in a semaphore register are monitored jointly to determine whether the hardware resource it represents is in use by a software thread. The bits in the same register bit location of all the semaphore registers are monitored jointly to determine the ID number of the software thread currently using the hardware resource. The limited-width test bus comprises of bit lines representing each semaphore registers and bit lines representing the contents of the semaphore registers. Semaphore protocol steps are used in addition to changes monitored by the limited-width test bus to determine current usage of each hardware resource and to identify the ID number of the software thread using a hardware resource.

 
Web www.patentalert.com

> Device-level address translation within a programmable non-volatile memory device

~ 00349