A controller 26 for a packet radio network 20 includes a processor 27 that, in turn, includes a plurality of processor resources 30A 30D for processing a plurality of packet classes. Each packet class has a different delay sensitivity associated therewith. The processor 27 allocates to each packet class at least a portion of at least one processor resource 30A 30D, the allocation being based on the delay sensitivities associated with each packet class. Each processor resource 30A 30D may have a processing threshold, and the processor 27 may determine, based upon arriving packets, whether at least one processor resource will exceed its processing threshold, thus defining at least one overloaded processor resource 30A. The processor 27 may reallocate at least a portion of at least one processor resource to process packets for the at least one overloaded processor resource 30A thereby defining at least one reallocated processor resource 30D.