Phase-locked loop (PLL) methods and apparatus are described for generating multiple output clocks synchronized to different frequencies of multiple input signals, wherein the multiple-output PLL employs a single voltage controlled oscillator (VCO). In an embodiment, the base module generates signals with a controlled frequency, multiple equidistant phase, and reduced duty cycles. Frequency dividers using barrel-shifters driven by an early-late detector combined with a left/right "one hot" shift-register or driven by an early-late detector combined with up-down counter/decoder are also disclosed.