The present invention relates to a semiconductor device fabrication method, which includes forming an inter metal dielectric on a semiconductor substrate having wirings and planarizing the inter metal dielectric through a chemical mechanical polishing, wherein the inter metal dielectric is formed by carrying out at least one cycle of depositing polycrystalline silicon, plasma-processing the polycrystalline silicon, and oxidizing the polycrystalline silicon.

 
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> Self aligned compact bipolar junction transistor layout and method of making same

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