A processor includes a set of registers, each individually addressable
using a corresponding register identification, and plural virtual
registers, each individually addressable using a corresponding virtual
register identification. The processor transfers values between the set
of registers and the plural virtual registers under control of a transfer
operation. The processor can include a virtual register cache configured
to store multiple sets of virtual register values, such that each of the
multiple sets of virtual register values corresponds to a different
context. Each of the plural virtual registers can include a valid bit
that is reset on a context switch and set when a value is loaded from the
virtual register cache. The processor can include a virtual register
translation look-aside buffer for tracking the location of each set of
virtual register values associated with each context.