A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device and at least one splitter element. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. A splitter element is positioned on or off a memory module and includes three resistors in embodiments of the invention. Three resistors form a Y or D topology in embodiments of the invention. One or more splitter elements are coupled to one or more channels to allow for upgrades of memory modules in a memory system. An asymmetrical splitter topology allows for increasing the number of memory modules to more than two memory modules without adding splitter elements serially on each channel. Splitter elements allow for increasing the number of ranks of memory modules in a system, while also achieving many of the benefits associated with point-to-point topology.