A driver includes, in part, a delay chain having disposed therein a
multitude of accessible nodes, and a control logic coupled to the various
nodes of the delay chain to generate the signals applied to the gate
terminals of the PMOS and NMOS transistors disposed in the driver. The
nodes that are accessed and tapped may or may not be the successive nodes
disposed along the delay chain. Optionally four nodes of the delay chain
are tapped to supply signals to the control logic. Two of the nodes,
carrying in-phase signals, are tapped to generate a first signal, which
is used to generate a second signal driving the NMOS transistor. The
other two nodes, carrying in-phase signals, are tapped to generate a
third signal, which is used to generate a fourth signal driving the PMOS
transistor. The first signal is 180.degree. out-of-phase with respect to
the third signal.