A synchronous semiconductor memory device allows one memory bank to begin executing a data operation (e.g., reading data from a memory cell) while another memory bank is executing another data operation (e.g., writing data to a memory cell). The synchronous semiconductor memory device includes a write data path through which an input data signal is transmitted to the memory cell of a memory bank executing a write operation, and a read data path through which an output data signal is transmitted from the memory cell of a memory bank executing a read operation to an input/output pin. The read and write data paths are each connected to the memory banks via a common input/output line. The operation of the memory banks and the write and read data paths are synchronized, such that once a first memory bank begins executing either the write or read operation, a second memory bank may begin executing the other type of data operation after a predetermined time delay has elapsed, while the first memory bank is still executing its data operation.