A data processor comprising: a register memory comprising an array of
memory cells extending in two dimensions, the cells being located on rows
in the first dimension and columns in the second dimension, each cell
being addressable by means of an instruction specifying a pair of
coordinates that identify the row and column of the cell in the array;
and a processing unit capable of executing instructions that operate on a
plurality of memory cells in the register, the instructions identifying
the plurality of cells by means of a first instruction part specifying a
pair of coordinates that identify a first cell in the array, and a second
instruction part that identifies the configuration of the plurality of
cells relative to the first cell; the data processor being arranged to
interpret a first form of second instruction part as specifying a first
group of cells all of which are located in the same row but in different
columns, and to interpret a second form of second instruction part as
specifying a first group of cells all of which are located in the same
column but in different rows.