An integrated circuit buffer device comprising a receiver circuit to receive control information and address information. A first interface portion provides at least a first control signal that specifies a write operation to a first memory device. The first control signal corresponds to the control information. A second interface portion provides a first address to the first memory device. The first address corresponds to the address information. The first address specifies a memory location for the write operation to the first memory device. A third interface portion provides a first signal to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion provides at least a second control signal that specifies a write operation to a second memory device. The second control signal corresponds to the control information. A fifth interface portion provides a second address to the second memory device. The second address corresponds to the address information. The second address specifies a memory location for the write operation to the second memory device. A sixth interface portion provides a second signal to the second memory device. The second signal synchronizes communication of the second control signal from the integrated circuit buffer device to the second memory device.