A power control signal controls a low-power mode, a USB connection, and an asynchronous reset function for a bridge circuit. Another power control signal controls both a high power mode and a low power mode for an attached device. The two power control signals reduce the number of pins required on the bridge circuit for controlling its own power related operations and power related operations of the attached device.

 
Web www.patentalert.com

> Low latency FIFO circuit for mixed clock systems

~ 00335