A link module architecture is disclosed for use with a multi-core central processing unit having a cross bar switch. The link module comprises timing recovery circuitry operably coupled to the central processing unit, wherein the timing recovery circuitry is positioned proximate to the cross bar switch. The link module further comprises a bit receiver operably coupled to the central processing unit, and a bit output driver operably coupled to the central processing unit. The bit receiver, preferably comprising a wide bandwidth amplifier, and the bit driver are preferably integrated with a sea of on-chip RAM.