A method and apparatus is described which allows efficient optimization of integrated circuit designs. By performing a global analysis of the circuit and identifying bottleneck nodes, optimization focuses on the nodes most likely to generate the highest return on investment and those that have the highest room for improvement. The identification of bottleneck nodes is seamlessly integrated into the timing analysis of the circuit design. Nodes are given a bottleneck number, which represents how important they are in meeting the objective function. By optimizing in order of highest bottleneck number, the optimization process converges quickly and will not get side-tracked by paths that cannot be improved.