A method and apparatus folds a circuit having a plurality of transistors. The folding includes: (a) determining a number of folds to realize a desired layout of the circuit based on a netlist of the circuit, a folded circuit having a number of fingers corresponding to the number of folds; (b) creating a single-finger layout for the circuit, the single-finger layout including a respective smaller transistor for each of the original transistors, each of the smaller transistors having a size which is an original size of the corresponding original transistor divided by the number of the fingers, the smaller transistors in the single-finger layout having an arrangement the same as an original arrangement of the original transistors in the circuit; and (c) tiling the single-finger layout for the number of folds such that each single-finger layout abuts an adjacent single-finger layout.

 
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> Providing instruction execution hints to a processor using break instructions

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