A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bridge circuit connecting the first and second buses. The bus bridge circuit has a first transfer controller, responsive to an access request from the first bus to the second bus, for obtaining a bus right of the second bus, and a second transfer controller, responsive to an access request from the second bus to the first bus, for obtaining a bus right of the first bus. The second bus has a first path connecting the second bus slave module and the first transfer controller and a second path connecting the second bus master module and the second transfer controller.