Disclosed is a deinterleaving apparatus and a method for a digital communication system which can be simply implemented. The deinterleaving apparatus has a row counter for increasing a row counting value based on input data, a column counter for increasing a column counting value every row period set in the row counter, a plurality of synchronous counters corresponding to the row period, and for increasing a synchronous counting value every column period set in the column counter, an offset memory for storing offset values set in correspondence to interleaving delay depths of the input data by channel, and a deinterleaver memory for storing the input data at a write address generated based on the offset value. The input data stored in the deinterleaver memory is read at a read address generated based on the synchronous counting value. Accordingly, simple implementation of the deinterleaving apparatus is enabled.

 
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> Measurement circuit and method for serially merging single-ended signals to analyze them

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