A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared. One of the faults is selected, and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by the implication operation, and a propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by the implication operation. A sequence formed by v1 and v2 is registered with a test pattern list, and the described operations are repeated until there remains no unprocessed fault in the fault list.

 
Web www.patentalert.com

> Navigation system and method therefor

~ 00327