An input/output (I/O) buffer having an input mode and coupled between first and second supply voltages includes a PMOS pull-up transistor fabricated in an nwell, and a gate bias control transistor coupled to the gate of the PMOS pull-up transistor for coupling the gate of the PMOS pull-up transistor to an input/output node in response to an input signal having a voltage greater than approximately the first supply voltage. A well bias control circuit is coupled to the PMOS pull-up transistor and to a well drive transistor to couple the nwell terminal to the first supply voltage in response to the input signal having a voltage approximately equal to or less than the first supply voltage.

 
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> Method and apparatus for implementing frame header alterations using byte-wise arithmetic logic units

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