A method and system for repairing defective memory in a semiconductor
chip. The chip has memory locations, redundant memory, and a central
location for ordered fuses. The ordered fuses identify in compressed
format defective sections of the memory locations. The defective sections
are replaceable by sections of the redundant memory. The ordered fuses
have an associated a fuse bit pattern of bits which sequentially
represents the defective sections in the compressed format. The method
and system determines the order in which the memory locations are wired
together; designs a shift register of latches through the memory
locations in accordance with the order in which the memory locations are
wired together; and associates each of the latches with a corresponding
bit of an uncompressed bit pattern from which the fuse bit pattern is
derived. The uncompressed bit pattern comprises a sequence of bits,
representing the defective sections in uncompressed format.