A digital camera includes an image control processing section in which a memory controller controls a video memory, a bus arbitrator, a display sequencer, and a timing adjusting section. Image data are read out of the video memory and fed to a data corrector. The display sequencer adjusts a sampling order in accordance with the combination of luminance data and color data constituting the image data, while varying a packet size. The bus arbitrator arbitrates access requests in accordance with priority to thereby reduce the occupation ratio of a bus. The data corrector restores and processes the image data and then delivers them to a buffer memory included in the timing adjusting section.

 
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> Active matrix in-plane switching type liquid crystal display and compensator arrangement

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