A load balancing mechanism and technique that monitors a memory interface associated with a processor resource in a processor pool associated with at least one node of a computer network. The monitoring determines the actual load activity executed by the processor during a specified period of time. The mechanism comprises a hardware access monitor configured to determine the true activity of each processor resource. The access monitor tracks certain memory requests over the memory interface and stores the requests in a counter assigned to each processor. The access monitor then collects statistics from each processor resource of the pool and provides those statistics to a central load balancing resource for use when determining assignment of loads (tasks) to the various processor resources.