A common electrode line for plating is used for forming conductive patterns of a plurality of circuit substrates on a main substrate. The main substrate has a cut line for dividing one and the other circuit substrates and a plurality of through holes formed on the one and the other circuit substrates along the cut line. The common electrode lines for plating includes first common electrode lines formed on one side of the main substrate, and second common electrode lines formed on the other side of the main substrate. Each first common electrode line extends from one through hole formed on the one circuit substrate to one through hole formed on the other circuit substrate. Each second common electrode line extends from the one through hole formed on the one circuit substrate to another through hole formed on the other circuit substrate.