The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable. Similarly, if the testing process determines that the failures in the embedded memory array can be repaired, then a signal is provided directly to an external testing apparatus indicating that the embedded memory array is repairable. Lastly, if no failures are found in an embedded memory array, then a signal is provided to an external testing apparatus indicating that the embedded memory array contains no failures. Based upon these status signals, the external testing device can determine which set of data (i.e., repair data and/or failure map data) to off-load from each embedded memory array and which sets of data to disregard, thereby reducing the memory test time for a device. Another aspect of the disclosed method and apparatus is a data flow control unit that controls the flow of input and output data to each of the embedded memory arrays. This device broadcasts the test program to each of the embedded memory arrays at the same time thereby enabling the simultaneous testing of multiple embedded memory arrays. Yet another aspect of the disclosed method and apparatus is a shorthand notation for indicating where memory failures occur within an embedded memory array.