A method of testing a plurality of memory blocks of an integrated circuit
in parallel, wherein each memory block comprising data bit storage cells
in an array of rows and columns, and wherein each row of storage cells is
addressable to store a word of data bits having a width determined by the
number of columns of the array, comprises the steps of: writing test data
words in parallel to the rows of the plurality of memory blocks; reading
out test data words in parallel from the rows of the plurality of memory
blocks to a corresponding plurality of on-chip data word comparators;
presenting corresponding expected data words in parallel to the plurality
of on-chip data word comparators for comparison with the read out data
words of the corresponding memory blocks; concurrently comparing
corresponding data bits of the read out data words and expected data
words in corresponding data bit comparators to generate a column status
bit for each data bit comparison; latching the column status bit of a
mismatch bit comparison in the corresponding data word comparator; and
reading the column status bits of each on-chip data word comparator.