A method of fabricating a semiconductor device is provided. An interlayer
dielectric layer is formed on one or more semiconductor layers (402). One
or more feature regions are formed in the interlayer dielectric layer
(404). A first conductive layer is formed in at least a portion of the
feature regions and on the interlayer dielectric layer (406)). A first
anneal is performed that promotes grain growth of the first conductive
layer (408). An additional conductive layer is formed on the first
conductive layer (410) and an additional anneal is performed (412) that
promotes grain growth of the additional conductive layer and further
promotes grain size growth of the first conductive layer. Additional
conductive layers can be formed and annealed until a sufficient
overburden amount has been obtained. Subsequently, a planarization
process is performed that removes excess conductive material and thereby
forms and isolates conductive features in the semiconductor device (414).