A processor with instructions to operate on different data types stored in
a single logical register file. According to one embodiment of the
invention, a processor includes a number of physical registers, a memory
unit, and a decode/execution unit. The memory unit is to make the number
of physical registers appear to software as a single software-visible
register file. The decode/execution unit is to execute on the contents of
the single software-visible register file instructions of a first
instruction type and of a second instruction type, wherein the single
software-visible register file is to be operated as a flat register file
during execution of instructions of the second instruction type and as a
stack referenced register file during execution of instructions of the
first instruction type.