A power amplification circuit includes a PWM signal generating portion operable to produce from an input signal first and second PWM signals having complementary variations in their respective pulse widths, a first delaying portion operable to delay the first PWM signal by a first time to produce a first delayed PWM signal, a first switching amplifier operable to perform a switching operation in response to the first delayed PWM signal to subject the first delayed PWM signal to power amplification to produce a first output signal, and to supply the first output signal to a circuit load, a second delaying portion operable to delay the second PWM signal by a second time different from the first time to produce a second delayed PWM signal, and a second switching amplifier operable to perform a switching operation in response to the second delayed PWM signal to subject the second delayed PWM signal to power amplification to produce a second output signal, and to supply the second output signal to the circuit load.

 
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> Constant frequency duty cycle independent synthetic ripple regulator

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