There is provided a RAS time control circuit for use in a semiconductor memory device. The RAS time control circuit includes a counter for counting the number of external clocks, a comparator for comparing the counted clock number with a preset comparison reference value, a RAS controller for determining a delay time of an internal RAS signal from the comparison result of the comparator, and an internal RAS generator for maintaining an internal RAS signal according to an instruction of the RAS controller.

 
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> Refresh control circuit and method for multi-bank structure DRAM

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