In a display device comprising a display panel driven in an active matrix scheme, a display control circuit generating image data and clock, and at least one source driver acquiring the image data in response to the clock and supplying image signals based on the image data to the display panel, the present invention generates dummy data in stead of the image data, makes the at least one source driver acquire the dummy data, reads out the dummy data acquired by the at least one source driver, compares the dummy data read out from the at least one source driver with the dummy data in an original state, and adjust delay time of the clock to the image signal in accordance with the comparison result, so as to reduce flicker in an image displayed by the display device due to timing difference between the image data and the clock.

 
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> Memory module having a memory controller to interface with a system bus

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