A method, apparatus, system, and signal-bearing medium that in an embodiment use a requested address for an intent seize and a processor associated with the intent seize to determine a hash table entry. If the requested address is not found in the hash table, all hash tables for all processors are updated to anchor to the requested address. Non-intent seizes use a hash table associated with a designated processor, regardless of whether the designated processor initiated the non-intent seize. In this way, in an embodiment modified, cache line interventions may eliminated for intent seizes.

 
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< Storage having logical partitioning capability and systems which include the storage

< Prefetching hints

> Processor state reintegration using bridge direct memory access controller

> Profiling of computer programs executing in virtual memory systems

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