A non-volatile memory is described that utilizes a cache read mode of
operation, where a next page of memory is being read/sensed from the
memory array by the sense amplifiers while a previously read page of
memory is being read from the memory I/O buffer, wherein the next page is
user selected. This random cache read mode allows for a memory with a
random page read capability, in which the address of the next page of
data to be read is user selectable, which benefits from the low latency
of a cache read mode of operation due to concurrent data sensing and data
I/O.