A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

 
Web www.patentalert.com

< Methods for driving bistable electro-optic displays, and apparatus for use therein

< Correcting variations in the intensity of light within an illumination field without distorting the telecentricity of the light

> Placement of lumiphores within a light emitting resonator in a visual display with electro-optical addressing architecture

> Method and device for photothermal imaging tiny metal particles immersed in a given medium

~ 00294