A register file architecture in a general purpose digital signal processor
(DSP) supports alignment independent SIMD (Single Instruction/Multiple
Data) operations. The register file architecture includes a register pair
and an alignment multiplexer. Two 32 bit grouped words may be loaded into
the register pair. Each grouped word includes four 8 bit operands. The
alignment state of the 32 bit words may be determined by the two least
significant bits (LSBs) of the pointer addresses of the grouped words.
These LSBs are used to control the alignment MUX to select n operands
from the two 32 bit grouped words and output an aligned 32 bit grouped
word to execution units for parallel processing.