A method and apparatus for optimizing register allocation during
scheduling and execution of program code in a hardware environment. The
program code can be compiled to optimize execution given predetermined
hardware constraints. The hardware constraints can include the number of
register read and write operations that can be performed in a given
processor pass. The optimizer can initially schedule the program using
virtual registers and a goal of minimizing the amount of active registers
at any time. The optimizer reschedules the program to assign the virtual
registers to actual physical registers in a manner that minimizes the
number of processor passes used to execute the program.