Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The MOSFET can be programmed by operation in a reverse direction trapping charge in the gate insulator adjacent to the first source/drain region such that the programmed MOSFET operates at reduced drain source current when read in a forward direction.

 
Web www.patentalert.com

< Electrical conductors comprising single-wall carbon nanotubes

< Method of secure personal identification, information processing, and precise point of contact location and timing

> Energy-protective composition comprising adenosine phosphates

> Portable navigation and communication systems

~ 00290