Methods of implementing a static memory cell compliant with the requirements of phase shift masks. A phase shift compliant memory cell is generated by implementing a single bit line, two word lines, first and second cross-coupled logic gates, and first and second pass gates. The logic gates and pass gates include transistors that use a fabrication layer (e.g., polysilicon) to implement the gate nodes of the transistors. All of these gate nodes extend substantially in a first direction. Throughout the static memory cell, the fabrication layer is implemented without T-shaped polygons in compliance with the requirements for a phase shift mask. In some embodiments, the static memory cell is a configuration memory cell for a PLD, and the method includes implementing an interconnection between at least one of the first and second storage nodes and programmable logic elements of the PLD.