A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.

 
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< System and method for using hardware performance monitors to evaluate and modify the behavior of an application during execution of the application

< Method and apparatus for enhancing scheduling in an advanced microprocessor

> Multiple clock domain microprocessor

> Multi-port memory device having serial I/O interface

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